While manufacturing integrated circuits (ICs), a deposition step is usually performed on the semiconductor wafer and a conductive layer, a semi-conductive layer and a dielectric layer are removed from the deposition layer. Basically, after a material is deposited on the semiconductor wafer, the surface of the semiconductor wafer become uneven and thus a planarization step need to be exerted on the surface of the semiconductor wafer. The planarization step is used to remove the undesired topography structures, such as rough surface, scratches, polluted portions and surface defects.
A Chemical Mechanical Polishing (CMP) is a planarization technique for the semiconductor wafer where the semiconductor wafer is located in the CMP device and contacts the polishing pad. The polishing slurry with chemical-base feature is introduced to the gap between wafer and the polishing pad so that the chemical and mechanical functions exerted between the slurry and the polishing pad for planarizing and polishing the wafer surface.
Even if the CMP technique is widely used in semiconductor process for a global planarization, however, it is necessary to overcome the issues including residual stresses, scratches and the clean step followed by planarization step while the CMP process is employed in the multiple layer structure with the copper and low-k materials.
As shown in FIG. 11, it is a schematic view of cavities 911 within the copper conductive wire 91 by using a conventional planarization structure after performing a chemical-mechanical polishing method on a wafer 90. Further, there are cavities 911 in the oxide layer 92 between the copper conductive wire 91 and the wafer 90, resulting in the defects of the wafer. Consequently, there is a need to develop a novel system and method to solve the aforementioned problems.